1. Field of the Invention
The present invention relates to a computer-aided design (CAD) method, a CAD tool, a set of photomasks produced by the CAD method, a semiconductor integrated circuit manufactured employing the set of photomasks and a computer program product for executing the CAD method, and in particular to a configuration for arranging via-holes at a termination of a interconnection, which implements a multi-level interconnection.
2. Description of the Related Art
Recently, with the miniaturization of the feature size of semiconductor integrated circuits, it becomes difficult to establish a geometry of metallic wirings configured to interconnect between circuit elements as designed. For example, a termination of a metallic wiring on one wiring level in a multi-level interconnection becomes shorter than the length of normally designed configuration. And because of misalignment in overlay accuracy from upper to lower wiring levels, in the photolithography process, such a phenomenon (shortening) occurs, as an upper metallic wiring does not reach the position of a via-hole which is supposed to connect the upper metallic wiring to a lower metallic wiring, and defective connection is generated. And, with advancements in miniaturization of semiconductor integrated circuits, since it becomes difficult to bury metallic material in a small via-hole, wiring failures such as disconnection and poor contact occur.
Therefore, to solve these problems, a CAD method for preventing defective connection is proposed, in which four extension regions are provided in front and rear ends and on right and left sides of a rectangular space disposed at an end (a termination) of a lower metallic wiring, a via-hole connecting the subject (lower) and upper wiring levels penetrates to the rectangular space, and upper metallic wiring can reach the via-hole, even if shorting between the subject (lower) and upper wiring levels does occur.
However, according to the above-mentioned CAD method, where a wiring grid (wiring lattice) is first set at each wiring level and metallic wirings are arranged in reference to the wiring grid, wiring efficiency becomes low because the extension regions occupy the triple wiring lattices (the wiring grid) located adjacent both sides of the corresponding metallic wiring. Especially, in a case where more than two via plugs were formed in the termination of metallic wiring, extension regions in a large area spanning over more than two via plugs must be established, and the extension regions an even larger space to include additional wiring grids located adjacent on both sides of the corresponding metallic wiring, this causes even lowered wiring efficiency.